This disclosure relates generally to semiconductor testing, and more particularly to eye diagram capture devices, systems, and methods, and even more particularly to an on-chip eye diagram capture device, system and method for a chip-on-wafer-on-substrate (CoWoS) flow.
Eye diagrams provide a useful tool in evaluating the quality of a digital signal. To construct an eye diagram, the digital signal is displayed on an oscilloscope at the signal bit rate, whereby individual instances of the digital waveform are superimposed upon each other. The display has the appearance of an eye. The size and shape of the clear area around the center of the eye provide an indication of the quality of the digital signal.
In three-dimensional integrated circuit (3D-IC) technology, it is sometimes impossible to display eye diagrams using conventional techniques during the wafer stage, since the signal speed is typically too high. Designers need to bond out the high speed IO signals and connect to an oscilloscope in order to display the eye diagram. In 3D-IC technology for CoWoS applications, a wide bus connection may be made available; however, it can be difficult to monitor all the bus eye diagrams due to lack of available controlled collapse chip connection (C4) solder bump resources and limited chip area. In cases where the high speed IO interface can be connected out, such connection may impact high speed IO performance for normal operating modes. If eye diagrams cannot be displayed, the analog performance parameters of the device cannot be fine-tuned to obtain optimum performance for a device.